5G Layer1 SOC IP engineer
Qualifications:
- Engineer motivated in developing ASIC and FPGA. VHDL/Verilog knowhow and RTL coding and modeling experience
- Engineer motivated in signal processing
- Complete understanding of the SoC (ASIC/FPGA) design flow and process
- Knowledge of SoC design and verification tools (SystemVerilog / UVM)
- Good spoken and written technical English