5G Layer1 SOC IP/FPGA sr engineer
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Over 5 years working experience in developing ASIC and FPGA. Excellent VHDL/Verilog knowhow and RTL coding and modeling experience.
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Complete understanding of the SoC (ASIC/FPGA) design flow and process.
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Knowledge of SoC design and verification tools (SystemVerilog / UVM).
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Solid background in cellular networks and 2G, 3G and LTE technology.
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Good spoken and written technical English