DFE FPGA RTL Development&Verification Lead Engineer
Thanks for your interest in the DFE FPGA RTL Development&Verification Lead Engineer position.
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As a lead member of the SoC DFE team, the candidate will be a key contributor for DFE boards’ development/verification, with the focus on the Digital Intermediate Frequency (DIF), Digital Pre-Distortion (DPD) and Crest Factor Reduction (CSR). The candidates will contribute to the Design/verification strategy, Design/verification specification, in detail:
-Will be responsible for building of FPGA/ASIC verification environment, design of the test cases concerning codes/features coverage
-Will be responsible for FPGA/ASIC RTL coding/timing optimization/low power design/matlab algorithm model.
1. Education background: Master or above. Major in Computer Science, Telecommunication Engineering or related.
2. Specific Skills, knowledge and competencies:
- 8+ years with FPGA/ASIC development or verification experience, familiar with UVM, system Verilog, and Linux shell. With good understanding of FPGA verification’s flow and strategy.
- Having experience in RTL or related domains’ verification, such as writing test plan, test case executions, UVM environment building, automated regression simulation and result collection. Familiar with how to increase RTL code coverage, feature coverage, functional coverage.
- With deep understanding for digital signal processing technique. Good knowledge with wireless system architecture (UMTS, LTE, etc.).
3. General competencies:
- Strong communication skill.
- Highly responsible, self-motivated and proactive working attitude.
- Good team work spirit and willing to contribute to the team’s success
- Capable of managing changes and multi-tasks during the R&D phase
4. Language Ability: Fluent in both oral and written English
