DFE FPGA RTL Development&Verification Senior Engineer
As a member of SoC DFE R&D team, the candidate will be a key contributor for DFE development/verification, with the focus on Digital Intermediate Frequency (DIF), Digital Pre-Distortion (DPD) and Crest Factor Reduction (CFR) including the related modules test. The capable candidates will contribute to the Design/verification strategy, Design/verification specification.
-Will be responsible for building of FPGA/ASIC verification environment, design of the test cases concerning codes/features coverage
-Will be responsible for FPGA/ASIC RTL coding/timing optimization/low power design/matlab algorithm model.