Engineer, SoC/IP, 5G L1
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VHDL/Verilog/SystemVerilog/UVM knowhow and some coding and modeling experience.
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Understanding of the SoC (ASIC/FPGA) design flow and process.
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Knowledge of SoC (ASIC/FPGA) design and verification tools.
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Fluent spoken and written English.We are looking for more experienced or newly graduated persons or persons in the middle of studies.